This invention relates to DRAMs having a new sensing architecture. In particular, the conventional two stage latching is reduced to a single, direct sensing by a global shared sense amplifier and latch. In this architecture a read datapath contains one and only one sense amplifier.
Today""s integrated circuits include a vast number of transistor devices formed in a semiconductor. Smaller devices are the key to enhance performance and to increase reliability. As devices are scaled down, however, the technology becomes more complex and new methods are needed to maintain the expected performance enhancement from one generation of devices to the next. In Dynamic Random Access Memories (DRAM) the improvement of the peripheral circuits is of importance. Today""s high performance systems demand high speed memory access as well as wide memory bandwidth.
Conventional DRAM macros with multiple DRAM arrays consist of two separate stage of sense amplifiers and the corresponding latches, one at each DRAM array and one for the overall macro. The first stage of sense amplifiers/latches located at each DRAM array is used for sensing (reading) of the DRAM cell signals and the sensed data is stored in the latches. There are as many number of sense amplifiers and latches as the number of bit-lines, one sense amplifier/latch for each bit-line. Each of the first stage latches at each array are used for (1) during a Read operation, writing back to the DRAM cell after first stage sensing, and holding the sensed data and passing the data via its bit-switches, through the global bit-lines, onto the corresponding second stage sense amplifier, shared among all the arrays in the macro, for outputting to the corresponding dataline and I/O buffer external to the array, (2) during a Write operation, receiving and holding the data through its bit-switches from the global bit-lines, originated from the external I/O buffer and dataline, and writing to the DRAM cell. Usually, for the reading/writing of a bit of DRAM data, there requires two corresponding bit-lines, two bit-switches and two global bit-lines, configured to operate in differential, complementary mode.
In a conventional DRAM macro with primary sense amplifier and secondary sense amplifier each array is connected through the column bit-switches to the (differential) global bit-lines and then to the secondary sense amplifiers and the data I/O. There is a precharge circuit for each global bit-line.
Only one array and a word-line are active at a given time in a macro. The column bit-switch is used for multiplexing a number of bit-lines to a global bit-line, so that sharing of a global bit-line among the different arrays and among multiple bit-lines of an array can take place. Typically, in conventional DRAM, a global bit-line is shared among 8-64 bit-lines, e.g. 4K bit-lines with 512 global bit-lines, 2K primary sense amplifier, the multiplexing is 8:1. In the case of no sharing of global bit-line among bit-lines, i.e. one bit-line for each global bit-line, the column bit-switches are used for connecting the global bit-lines to the corresponding bit-lines in a particular array.
It is the object of this invention to describe a DRAM architecture which is simpler than the present art, it is of higher performance than the present art, and offers wide bandwidth data in and output rates.
This invention describes a DRAM architecture and sensing scheme for a DRAM macro with multiple arrays, without the use of the first stage sense amplifiers and latches as in a conventional DRAM. The primary sense amplifier and latch in a conventional DRAM can be totally eliminated for each differential pair of bit-lines. Instead of the conventional two stage sensing scheme, namely using primary sensing and latching, and secondary sensing and latching; a single stage, direct sensing scheme is introduced. In the new scheme, there is no primary sense amplifier and latch, DRAM signal is buffered at the array level to the global bit-line, and is sensed and latched directly at the macro level by the shared global sense amplifier which is shared among all the arrays in the DRAM macro. The term xe2x80x9csense amplifierxe2x80x9d as used here, always includes latching as well. In the conventional approach, the DRAM signal has to go through two stages of sensing and sensing timing control (two separate steps to set sense amplifier latches), whereas in this scheme, the DRAM signal is sensed directly at the macro level by the shared global sense amplifier with only one stage of timing. For Write operation, the macro level shared sense amplifier and latch write to the DRAM cell directly, also without going through the two stages as in conventional approach where the primary sense amplifier and latch are involved. As a result, the control to read a DRAM data can be simplified with less margin of error and overall read access time and cycle time can be much reduced.
Buffers are located at each array to amplify the bit-line signals for the global bit-lines, and also isolate the bit-lines from the global bit-line loading and switching noises. In the buffer area, there are also the Read control devices to enable the buffers during a Read operation, and the Write control devices for enabling the writing path from global bit-lines to bit-lines during a Write operation. A buffer can be shared between two different bit-lines of two arrays by multiplexing. At the end(s) of the macro is the global sense amplifiers and latches shared among all the DRAM arrays for sensing, also is the write circuit for writing to the DRAM cells through the global bit-lines and bit-lines during the Write-back phase of a Read/Write-back operation, or during a Refresh operation, or during a Write operation.
The new scheme minimizes the global bit-line wire delay. Only one array and a word-line are active at a given time in a macro. There is no sharing of global bit-line among bit-lines, i.e. one bit-line for each global bit-line, the column bit-switches are used for connecting the global bit-lines to the corresponding bit-lines of a particular array. Each of the differential pair of bit-lines is connected to each of the corresponding pair of global bit-lines through a NFET device configured as a buffer (gate driven by bit-line and drain output to the global bit-line through a Read control NFET device) for Read operation. For Write operation, a global bit-line is connected to the corresponding bitline through a Write control device. Since there is no primary sense amplifier and latch, primary sensing data is not stored in the latch at the array, instead the DRAM signal, from one active bit-line and an adjacent inactive bit-line serving as reference signal, are amplified by the differential pair of buffers and in turn discharging the two corresponding precharged global bit-lines with two differential currents respectively. The two different currents, determined by the buffer gate voltage and passed through the source-drain of the two buffers, are developed on two different global bit-lines and create a differential voltage signal for the shared global sense amplifier at the other end. The differential voltage signal is sensed directly by the differential sense amplifier and stored at the global sense amplifier which also serving as a latch during a Read operation. During a Write operation, data is written from the shared global sense amplifier through the global-bitlines to the bit-lines and then the individual DRAM cell.
The gate of the buffer NFET is controlled by voltage developed on the bit-line from the DRAM cell after the word-line is activated. Only one word-line is activated through out the macro. The NFET (drain to source) discharges the voltage on the global bit-line, which has been precharged to high (Vdd), slightly or heavily depending whether the DRAM cell stored a 0 or a 1. The gate voltage of the two different states (0 or 1), determines the drain-to-source current (Ids) through the NFET and hence the rate of discharging the global bit-line voltage. The other differential (inactive) bit-line is held at Vdd/2, assuming Vdd/2 sensing, which the bit-lines are precharged to Vdd/2. The differential signal on the two differential global bit-line is sensed by the shared, global differential sense amplifier at the other end of the DRAM macro, producing a corresponding logic 1 or 0 at the output.
For each Read operation, all the bits of the DRAM cells (N bits) controlled by the same word-line are read to the N shared global sense amplifiers. For Write-back operation, the N bits are written back to DRAM cells by the shared global sense amplifier. For each Write operation, N bits of data are written to the DRAM cells via the N global bit-lines. For Refresh operation, the N bits of data of a word-line are read to the shared global sense amplifiers and stored in the latches, and then written back to the corresponding DRAM cells by the same shared global sense amplifiers.
The single stage direct sensing scheme resulted in faster Read operation (smaller Read latency), since two separate xe2x80x9csense amplifier settingxe2x80x9d control steps required for the two stages sensing increase the Read speed compared to this single stage sensing scheme. Further, the number of FET""s used in the direct sensing is smaller than that required by the first stage of the two stage conventional sensing, hence resulted in smaller DRAM area.